DATA_END_BIT_ERR_SIGNAL_EN=Val_0x0, DATA_TOUT_ERR_SIGNAL_EN=Val_0x0, BOOT_ACK_ERR_SIGNAL_EN=Val_0x0, CMD_END_BIT_ERR_SIGNAL_EN=Val_0x0, CMD_CRC_ERR_SIGNAL_EN=Val_0x0, CMD_IDX_ERR_SIGNAL_EN=Val_0x0, CMD_TOUT_ERR_SIGNAL_EN=Val_0x0, DATA_CRC_ERR_SIGNAL_EN=Val_0x0, RESP_ERR_SIGNAL_EN=Val_0x0, ADMA_ERR_SIGNAL_EN=Val_0x0, AUTO_CMD_ERR_SIGNAL_EN=Val_0x0, CUR_LMT_ERR_SIGNAL_EN=Val_0x0
Error Interrupt Signal Enable Register
| CMD_TOUT_ERR_SIGNAL_EN | Command Timeout Error Signal Enable (SD or eMMC mode only). 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| CMD_CRC_ERR_SIGNAL_EN | Command CRC Error Signal Enable (SD or eMMC mode only). 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| CMD_END_BIT_ERR_SIGNAL_EN | Command End Bit Error Signal Enable (SD or eMMC mode only). 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| CMD_IDX_ERR_SIGNAL_EN | Command Index Error Signal Enable (SD or eMMC mode only). 0 (Val_0x0): No error 1 (Val_0x1): Error |
| DATA_TOUT_ERR_SIGNAL_EN | Data Timeout Error Signal Enable (SD or eMMC mode only). 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| DATA_CRC_ERR_SIGNAL_EN | Data CRC Error Signal Enable (SD or eMMC mode only). 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| DATA_END_BIT_ERR_SIGNAL_EN | Data End Bit Error Signal Enable (SD or eMMC mode only). 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| CUR_LMT_ERR_SIGNAL_EN | Current Limit Error Signal Enable. 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| AUTO_CMD_ERR_SIGNAL_EN | Auto CMD Error Signal Enable (SD or eMMC mode only). 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| ADMA_ERR_SIGNAL_EN | ADMA Error Signal Enable. 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| RESP_ERR_SIGNAL_EN | Response Error Signal Enable (SD mode only). 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |
| BOOT_ACK_ERR_SIGNAL_EN | Boot Acknowledgment Error (eMMC mode only). Setting this bit to 0x1 enables generating interrupt signal when Boot Acknowledgement Error in the SDMMC_ERROR_INT_STAT_R register is set. 0 (Val_0x0): Masked 1 (Val_0x1): Enabled |